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Polling and Interrupts

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Polling

The system can repeatedly and constantly check to see whether a change has occurred with a device (eg. Keyboard). This method is called polling, and is simple to design and implement, but usually inefficient.

Interrupts

When there is a change, the device can alert the processor to this change, which can then handle it once it’s ready by running an Interrupt Service Routine (ISR).

State Preservation

An interrupt could occur at any time, and the state of the processor when this happens is unpredictable. As such, the ISR must ensure that the state is preserved so that execution can continue as if the interrupt had not occurred. This means that the ISR must ensure that:

  • The PC contains the address of the instruction that was about to be executed before the interrupt occurred.
  • All general-purpose registers (R0-R15) must retain their values.
  • The status register (CPSR) must retain its value.

Handling an Interrupt Request (IRQ)

When an IRQ is received, the following steps are followed:

  • The address of the next instruction (+4) is moved into the Link Register (LR/R14).
  • The status register is moved to the “Saved Program Status Register” (SPSR <= CPSR).
  • IRQ is disabled by setting bit 7 of the CPSR to 1.
  • The PC is set to 0x18.

Info

There is an obscure feature in ARM wherein any data operation that sets flags and has the PC as the destination register will copy SPSR into CPSR. (eg. SUBS PC, LR, #4)

Interrupts from Multiple Sources

If there are multiple devices capable of triggering an IRQ, it may be helpful to be able to:

  • Allow interrupts from certain devices.
  • Determine which device has caused an interrupt.

To achieve this, two memory-mapped registers, connected to the data bus, are introduced for each (xth) device, IRq_x and IEn_x. The processor can write to IEn to enable interrupts for that device, and can read from IRq to determine which device triggered the interrupt.

By determining which device caused an interrupt, the correct ISR for that device can be executed.

Protecting Hardware and Memory

In order to restrict access to hardware and memory, the processor tracks whether it is in “User” mode or “IRQ” mode. A Memory Management Unit (MMU) between the processor and memory restricts access to certain memory regions based on the current processor mode. The processor mode is contained in bits 4-0 of the CPSR:

  • 10000 is “user mode”.
  • 10010 is “IRQ mode”.
  • 10011 is “supervisor mode” (kernel-like level, for System Calls).

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