Synthesis

Synthesis of Assignment §

All assign statements will always be synthesised into a combinatorial block. In some cases, it may be easy to see the exact circuit that will result from an assign statement. For example,

assign signal = X ? Y : Z

will synthesise to a 2:1 multiplexer.

Unlike assign statements, always blocks may be synthesised as either combinatorial or sequential circuits. If the sensitivity list does not contain any clock-like signal (indicated by posedge or negedge sensitivities), then it will result in a combinatorial circuit.

Limitations in Synthesis §

Some Verilog code cannot be synthesised into hardware, and is only available during simulation. For example, #100 cannot be synthesised, as an method to accurately delay for 100ns does not exist in the hardware. Equally, some more complex operations may be unavailable due to the number of different possible implementations. For example, multiplication and division (* and / operators) can be implemented in hardware in many different ways, and the synthesiser does not know which to use. As such, any logic for these operations must be implemented by the designer.