Modules in structural Verilog map any number of inputs to any number of outputs.

Defining Modules

The inputs and outputs for a module must be defined in its header:

module Structural_Module(input clk, enable,
						 output out0, out1);

Multiple instances of a module can then be created within other modules:

Structural_Module example_instance(clock, en, out, carry);

Parameters can be specified in any order as such:

Structural_Module example_instance(
		.enable(en),
		.clk(clock),
		.out1(carry),
		.out0(out)
);

This is also generally more readable and so is often preferred.